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INTEGRATED CIRCUITS
DATA SHEET
TEA0675 Dual Dolby* B-type noise reduction circuit for playback applications
Preliminary specification Supersedes data of July 1993 File under Integrated Circuits, IC01 1996 Jun 07
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
FEATURES * Dual noise reduction (NR) channels * Head pre-amplifiers * Reverse head switching * Automatic Music Search (AMS) * Music scan * Equalization with electronically switched time constants * Dolby reference level = 387.5 mV * 24 pins * Improved EMC behaviour. GENERAL DESCRIPTION The TEA0675 is a bipolar integrated circuit that provides two channels of Dolby B noise reduction for playback applications in car radios. It includes head and equalization amplifiers with electronically switchable time constants. Furthermore it includes electronically switchable inputs for tape drivers with reverse heads. QUICK REFERENCE DATA SYMBOL VCC ICC S+N ------------N supply voltage supply current signal plus noise-to-noise ratio PARAMETER - 78 MIN. 7.6 - 26 84 TYP.
TEA0675
This device also detects pauses of music in the Automatic Music Search (AMS) scan mode, for applications with an intelligent controlled tape driver, or AMS-latch mode, for applications with a simple controlled tape driver. For both modes, the delay time can be fixed externally by a resistor. The device operates with power supplies in the range of 7.6 to 12 V, output overload level increasing with increase in supply voltage. Current drain varies with the following variables: supply voltage noise reduction on/off AMS on/off. Because of this current drain variation it is advisable to use a regulated power supply or a supply with a long time constant.
MAX. 12 31 -
UNIT V mA dB
ORDERING INFORMATION TYPE NUMBER TEA0675 TEA0675T PACKAGE NAME SDIP24 SO24 DESCRIPTION plastic shrink dual in-line package; 24 leads (400 mil) plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT234-1 SOT137-1
Remark Dolby*: Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby Laboratories Licensing Corporation.
1996 Jun 07
2
1996 Jun 07
handbook, full pagewidth
BLOCK DIAGRAM
180 headswitch input 21 10 F 470 pF 330 k 1 k 470 pF
10 F
AMS output NR 4.7 nF 120 s 10 nF 8.2 k 27 k 24 k 18 k 70 s ON 1.5 k EQ
Philips Semiconductors
10 F 180 k
330 nF 15 nF OFF
100 nF
output B
270 k
24
23
22
21
20
19
18
17
16
15
14
13
DOLBY B
EQ AMP. AMS PROCESSOR LOGIC POWER SUPPLY
PRE AMP.
LATCH AND RISE TIME
TEA0675
Dual Dolby* B-type noise reduction circuit for playback applications
3
DELAY TIME EQ AMP. 4 5 6 7 8 9 VCC PRE AMP. 1.5 k Rt ON 4.7 nF
(1)
LEVEL DETECTOR
DOLBY B
1
2
3
10
11
12
270 k 24 k 8.2 k 10 nF 330 k
10 F 180 k 15 nF OFF AMS
100 F 470 pF 1 k 180 10 F 470 pF
output A
330 nF
100 nF
(1) Switched to VCC for AMS-scan mode.
MED621
Preliminary specification
TEA0675
Fig.1 Block and application diagram.
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
PINNING SYMBOL OUTA INTA CONTRA HPA SCA TD EQA EQFA VCC INA1 Vref INA2 INB2 HS INB1 GND EQFB EQB AMSEQ SCB HPB CONTRB INTB OUTB PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DESCRIPTION output channel A integrating filter channel A control voltage channel A high-pass filter channel A side chain channel A delay time constant equalizing output channel A equalizing input channel A supply voltage input channel A1 (forward or reverse) reference voltage input channel A2 (reverse or forward) input channel B2 (reverse or forward) head switch input input channel B1 (forward or reverse) ground equalizing input channel B equalizing output channel B AMS output and EQ switch input side chain channel B high-pass filter channel B control voltage channel B integrating filter channel B output channel B Fig.2 Pin configuration.
handbook, halfpage
TEA0675
OUTA INTA CONTRA HPA SCA TD EQA EQFA VCC
1 2 3 4 5 6
24 OUTB 23 INTB 22 CONTRB 21 HPB 20 SCB 19 AMSEQ
TEA0675
7 8 9 18 EQB 17 EQFB 16 GND 15 INB1 14 HS 13 INB2
MED622
INA1 10 Vref 11 INA2 12
1996 Jun 07
4
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
FUNCTIONAL DESCRIPTION Noise Reduction (NR) is enabled when pin HPB is open-circuit and disabled when connected to GND via an 1.5 k resistor. Dolby B noise reduction only operates correctly if 0 dB Dolby level is adjusted at 387.5 mV. Automatic Music Search (AMS) scan mode is enabled when pin HPA is connected to VCC via an 1.5 k resistor and disabled when pin HPA is open-circuit. Switching AMS on, internally NR is switched OFF simultaneously (see Figs 5 and 6 for principle timing in AMS-scan mode). AMS-latch mode is enabled when pin HPA is connected to GND via an 1.5 k resistor and disabled when pin HPA is open-circuit. Switching AMS on, NR is switched off internally. In this mode the device detects a pause level signal, when a music level signal has appeared first (see Figs 7 and 8 for principle timing). Furthermore a longer rise time constant is supplied for suppressing the detection of plops on tape. The output signal at pin AMSEQ in this mode may be applied to drive a tape driver logic circuit.
TEA0675
Equalization time constant switching (70 s or 120 s) is achieved when pin AMSEQ is connected to GND via an 18 k resistor (120 s), or left open-circuit (70 s). This does not affect the AMS output signal during AMS mode (see Fig.1). Head switching is achieved when pin HS is connected (input IN2 active) to GND via a 27 k resistor, or left open-circuit (input IN1 active). The 10 F capacitor at pin HS sets the time constants for smooth switching. In AMS mode the signals of both channels are rectified and then added. This means, even if one channel signal appears inverted to the other channel, the normal AMS function is ensured. Pins HPB and HPA perform the function of a logic input for AMS, respectively NR mode switching in both channels and provide the frequency dependent feedback of the control chain amplifier in the corresponding channel. Thus it is important that no voltage is applied to pins HPB and HPA during NR on/AMS off mode, otherwise this will cause irregular NR characteristics.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC Vi tshort Tstg Tamb Ves supply voltage input voltage (except pin 11) pin 11 (Vref) to VCC short-circuiting duration storage temperature operating ambient temperature electrostatic handling voltage for all pins note 1 note 2 Notes 1. Human body model (1.5 k, 100 pF). 2. Machine model (0 , 200 pF). PARAMETER CONDITIONS 0 -0.3 - -55 -40 -2 -500 MIN. MAX. 14 +VCC 5 +150 +85 +2 +500 V V s C C kV V UNIT
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
CHARACTERISTICS VCC = 10 V; f = 20 Hz to 20 kHz; Tamb = 25 C; all levels are referenced to 387.5 mV (RMS) (0 dB) at test point (TP) pin OUTA or OUTB; see Fig.1; NR on/AMS off; EQ switch in the 70 s position; unless otherwise specified. SYMBOL VCC ICC m THD HR S+N ------------N PSRR fo PARAMETER supply voltage supply current channel matching total harmonic distortion (2nd and 3rd harmonic) headroom at output signal plus noise-to-noise ratio power supply ripple rejection frequency response; referenced to TP f = 1 kHz; Vo = 0 dB f = 10 kHz; Vo = 10 dB VCC = 7.6 V; THD = 1%; f = 1 kHz internal gain 40 dB, linear; CCIR/ARM weighted; decode mode; see Fig.25 Vi(rms) = 0.25 V; f = 1 kHz; see Fig.22 encode mode; see Fig.25 Vo = -25 dB; f = 0.2 kHz Vo = 0 dB; f = 1 kHz Vo = -25 dB; f = 1 kHz Vo = -25 dB; f = 5 kHz Vo = -35 dB; f = 10 kHz cs cc RL Gv channel separation crosstalk between active and inactive input load resistance at output voltage gain of pre-amplifier Vo = 10 dB; f = 1 kHz; see Fig.23 f = 1 kHz; Vo = 10 dB; NR off; see Fig.23 AC-coupled; f = 1 kHz; Vo = 12 dB; THD = 1% from pin INA1 or INA2 to pin EQFA and from pin INB1 or INB2 to pin EQFB; f = 1 kHz -22.9 -1.5 -17.8 -18.1 -24.4 57 70 10 29 -24.4 0 -19.3 -19.6 -25.9 63 77 - 30 -25.9 +1.5 -20.8 -21.1 -27.4 - - - 31 dB dB dB dB dB dB dB k dB CONDITIONS 7.6 - f = 1 kHz; Vo = 0 dB; NR off -0.5 - - 12 78 MIN. 10 26 - 0.08 0.15 - 84 TYP. 12 31 +0.5 0.15 0.3 - - MAX. UNIT V mA dB % % dB dB
52
57
-
dB
VI(offset)(DC) Ii(bias) REQ Ri Av
DC input offset voltage input bias current equalization resistor input resistance head inputs open-loop amplification pin INA1 or INA2 to pin EQA and pin INB1 or INB2 to pin EQB f = 10 kHz f = 400 Hz
- - 4.7 60
2 0.1 5.8 100
- 0.4 6.9 -
mV A k k
80 104
86 110
- -
dB dB
1996 Jun 07
6
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
SYMBOL Vref - VOUT PARAMETER DC output offset voltage at pins OUTA and OUTB DC output current output impedance equivalent input noise voltage (RMS value) AMS timing (DC level) DC offset voltage at pins OUTA and OUTB NR off; unweighted; f = 20 Hz to 20 kHz; Rsource = 0 resistor Rt connected to pin TD f = 900 MHz; Vi(rms)= 6 V; see Figs 26, 27 and 28 CONDITIONS NR off; pins INA1, INA2, INB1 and INB2 connected to Vref pin OUTA to ground pin OUTB to VCC Zo Vno(rms) MIN. -0.15 - TYP.
TEA0675
MAX. +0.15
UNIT V
IO
-2 0.3 - -
- - 80 0.7
- - 100 1.4
mA mA V
VTD EMC
VCC - 3 -
- 40
VCC -
V mV
Switching thresholds VNROFF INROFF INRON VHPB(max) HPA (PIN 4) VAMSlON IAMSlON VAMSsON IAMSsON IAMSOFF VHPA(max) pin voltage output current pin voltage input current pin current maximum voltage AMS off AMS-scan on AMS-latch on 0.19VCC - 0.75VCC - - - 0.23VCC -0.7 0.77VCC 0.8 open - 0.25VCC -1 0.81VCC 1 200 0.75VCC V mA V mA nA V voltage at HPB (pin 21) output current input current maximum voltage NR off NR off NR on 0.19VCC - - - 0.23VCC -0.7 open - 0.25VCC -1 200 0.75VCC V mA nA V
AMSEQ (PIN 19)
AMS output (AMS mode)
VOH IOH1 IOH2 td VOL IOL tr AM/P HIGH level output voltage HIGH level output current HIGH level output current minimum pulse width; delay time range LOW level output voltage LOW level output current minimum pulse width rise time signal level at output for AMS switching music to pause AMS-scan mode AMS-latch mode AMS mode; f = 10 kHz; note 2; see Fig.24 note 1 note 1 see Table 1 4 +10 +0.01 - - -0.02 2 130 -25 4.6 - - 5 -150 -1 V A mA ms V mA ms ms dB
23 to 160 - 0.1 - 6 150 -22 0.7 +1 10 170 -19
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
SYMBOL AP/M PARAMETER signal level at output for AMS switching pause to music CONDITIONS AMS mode; f = 10 kHz; -24 MIN. TYP. -21
TEA0675
MAX. -18
UNIT dB
EQ switch input (not AMS mode)
IEQ70 IEQ120 IEQth VHSW IHSW VHSW(HIGH) VHSW(LOW) Notes 1. In AMS off mode, pin AMSEQ is HIGH level, the equalization time constant will be switched by pulling approximately 200 A out of pin AMSEQ. This means for the device connected to pin AMSEQ, a restriction of input current at HIGH level less than 200 A during AMS off; otherwise the selection of the equalization time constant is disabled and fixed at 120 s. If the connected devices consume more than 200 A, this input has to be disconnected in AMS off mode. (To ensure switching, the currents for the different switched modes are specified with a tolerance of 50 A in Chapter "Characteristics".) For an application with a fixed EQ time constant of 120 s the equalizing network may be applied completely external. Change 8.2 k resistor to 14 k the internal resistor REQ = 5.8 k is short-circuited by fixing the EQ switch input at the 70 s position (IEQ70). 2. The high speed of the tape (FF, REW) at the tape head during AMS mode causes a transformation of level and frequency of the originally recorded signal. It means a boost of signal level of approximately 10 dB and more for recorded frequencies from 500 Hz up to 4 kHz. So the threshold level of -22 dB corresponds to signal levels in Play Back (PB) mode of approximately -32 dB. The AMS inputs for each channel are pin SCA and pin SCB. As the frequency spectrum is transformed by a factor of approximately 10 to 30 due to the higher tape speed in FF, REW, the high-pass filter (4.7 nF/24 k) removes the effect of offset voltages but does not affect the music search function. In the application circuit (Fig.1) the frequency response of the system between tape heads input, e.g. pins INA2 and INB2, to the AMS input pins SCA and SCB is constant over the whole frequency range (see Fig.3). 3. To activate the inputs IN1, pin HS might be left open-circuit. In this event the DC level at pin HS is 0.775VCC. input current input voltage threshold current time constant 70 s active note 1 load current +90 to -90 A VHSW = 0 to VCC inputs INA1 and INB1 active; note 3 inputs INA2 and INB2 active -150 - - -170
1 2VCC
- - -200 0.8VCC - + 0.5 - -
- -250 - - +170 VCC
1 2VCC
A A A V A V - 0.5 V
time constant 120 s active -1000
HEAD SWITCHING pin voltage input current HIGH level pin voltage LOW level pin voltage
0
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
Table 1 Blank delay time set by resistor Rt at pin TD RESISTOR VALUE Rt (k) 68 150 180 220 270 330 470 560 680 820 1000 General note DELAY TIME td TYP. (ms) 23 42 48 56 65 76 98 112 126 142 160
TEA0675
TOLERANCE (%) 20 15 15 15 10 10 10 10 10 10 10
It is recommended to switch off VCC with a gradient of 400 V/s at maximum to avoid plops on tape in the event of contact between tape and tape head while switching off.
handbook, full pagewidth
-20
MED623
(1)
(dB) -30
-40
(2)
-50
-60 102
103
104
(Hz)
105
(1) AMS threshold level for application circuit (Fig.1). (2) AMS threshold level for test circuit (Fig.24).
Fig.3 AMS threshold level.
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
Short description `music search' A system for `music search' mainly consists of a level and a time detection (see Fig.4). For adapting and decoupling the input signal will be amplified (A), then rectified (B) and smoothed with a time constant (C). So the voltage at (C) corresponds to the signal level and will be compared to the predefined pause level at the first comparator (D), the level detector. If the signal level becomes smaller than the pause level, the level detector changes its output signal. Due to the output level of the level detector the capacitor of the second time constant (E) will be charged,
TEA0675
respectively discharged. If the pause level of the input signal remains for a certain time, the voltage at the capacitor reaches a certain value, which corresponds to an equivalent time value. The voltage at the capacitor will be compared to a predefined time-equivalent voltage by the second comparator (F), the time detector. If the pause level of the input signal remains for this predefined time, the time detector changes its output level for `pause found' status.
handbook, full pagewidth
(A)
(B)
(C)
(D)
COMPARATOR 1
(E)
(F)
COMPARATOR 2
INPUT
t1
VI
t2
Vt
OUTPUT
AMPLIFIER
RECTIFIER
LEVEL DETECTOR
TIME DETECTOR
MED624
Fig.4 Integrated `music search' function.
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
Description of the principle timing diagram for AMS-scan mode without initial input signal (see Fig.5)
tr: rise time handbook, full pagewidth td: delay time tb: burst time tp: pause time tf: fall time tr tbAMS on
td tf
tpVin t
Vl Vl: voltage at level detector input pin 3 (CONTRA) t Vt upper threshold (hysteresis) Vt: voltage at time detector input pin 22 (CONTRB)
level threshold VREF
time threshold
t VAMSEQ 4.5 V output signal to microprocessor t0 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t
MED625
Fig.5 AMS-scan mode without initial input signal.
By activating AMS-scan mode, the AMS output level directly indicates whether the input level corresponds to a pause level (VAMSEQ = LOW) or not (VAMSEQ = HIGH). At t0 the AMS-scan mode is activated. Without a signal at Vin, the following initial procedure runs until the AMS output changes to LOW level: due to no signal at Vin the voltage at the level detector input VI (pin 3, CONTRA) remains below the level threshold and the second time constant will be discharged (time detector input Vt). When Vt passes the time threshold level, the time detector output changes to LOW level. Now the initial procedure is completed. If a signal burst appears at t3, the level detector input voltage rises immediately and causes its output to charge the second time constant, which supplies the input voltage Vt for the time detector. When Vt passes the upper
threshold level after the rise time tr (at t4), the AMS output changes to HIGH. If the signal burst ends at t5 the level detector input VI falls to its LOW level. When passing the level threshold at t6, the discharging of the second time constant begins. Now the circuit measures the delay time td, which is externally fixed by a resistor and defines the length of a pause to be detected. If no signal appears at Vin within the time interval td, the time detector output switches the AMS output to LOW level at t7. If a plop noise pulse appears at Vin (t8) with a pulse width less than the rise time tr > tb, the plop noise will not be detected as music. The AMS output remains LOW. Similarly the system handles `no music pulses' tp: when music appears at t11 with a small interruption at t13, this interruption will not affect the AMS output for tp < td.
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
Description of the principle timing diagram for AMS-scan mode with initial input signal (see Fig.6)
tr: rise time handbook, full pagewidth td: delay time tb: burst time tp: pause time tf: fall time Vin
AMS on
td tf
tbtpt
Vl Vl: voltage at level detector input pin 3 (CONTRA) t Vt upper threshold (hysteresis) Vt: voltage at time detector input pin 22 (CONTRB)
level threshold VREF
time threshold
t VAMSEQ 4.5 V output signal to microprocessor t t0 t1 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15
MED626
Fig.6 AMS-scan mode with initial input signal.
At t0 the AMS-scan mode is activated. With an input signal at Vin, the following initial procedure runs until the circuit gets a steady state status. Due to the signal at Vin the voltage at the level detector input VI (pin 3, CONTRA) slides to a value which is defined by a limiter. This voltage causes the level detector output charging the second time constant (time detector input Vt)
to its maximum voltage level at t1. Now the initial procedure is completed. The following behaviour does not differ from the description in Section "Description of the principle timing diagram for AMS-scan mode without initial input signal (see Fig.5)".
1996 Jun 07
12
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
Description of the principle timing diagram for AMS-latch mode without initial input signal (see Fig.7)
tr: rise pagewidth handbook, fulltime td: delay time tb: burst time tp: pause time tf: fall time
AMS on
tr
td tf
tbtpVin t
Vl Vl: voltage at level detector input pin 3 (CONTRA) t Vt upper threshold (hysteresis) Vt: voltage at time detector input pin 22 (CONTRB)
level threshold VREF
time threshold
t
internal latch status
H L t
VAMSEQ 4.5 V output signal to power FET t0 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t
MED627
Fig.7 AMS-latch mode without initial input signal.
This is similar to the description of the principle timing diagram from AMS-scan mode. It only differs in its initial behaviour and its rise time tr. (Please notice that the different tr does not occur in the principle timing diagrams for latch and scan mode). Running in AMS-latch mode, the circuit may be simply applied to drive a stop solenoid via a power FET. So the AMS output signal has not to be processed by a controller. Because there is no processor to make a decision whether there is a plop noise or not, for this mode the rise time tr is extended to approximately 150 ms. By activating AMS-latch mode the AMS output will not change to LOW level at t2 if there is no initial signal at Vin.
A latch forces the AMS output to be HIGH until a signal appears at Vin (t4). After t4 the latch will not affect the output any more until AMS-latch mode is started again. The existence of the latch appears necessary if the AMS output for example drives a stop solenoid via a power FET. The LOW output level will cause a drive of the stop solenoid. This would happen after a maximum time of td occurred without any input signal. If there is no music on tape for a long time (e.g. at tape end), the AMS mode would be activated repeatedly as long as there is no signal at Vin. Thus the circuit waits until first music appears before detecting the pauses.
1996 Jun 07
13
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
Description of the principle timing diagram for AMS-latch mode with initial input signal (see Fig.8)
r handbook, full pagewidth Vin
t : rise time td: delay time tb: burst time tp: pause time tf: fall time
AMS on
td tf
tbtpt
Vl Vl: voltage at level detector input pin 3 (CONTRA) t Vt upper threshold (hysteresis) Vt: voltage at time detector input pin 22 (CONTRB)
level threshold VREF
time threshold
t
internal latch status
H L
t
VAMSEQ 4.5 V output signal to power FET t t0 t1 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15
MED628
Fig.8 AMS-latch mode with initial input signal.
This is similar to the description in Section "Description of the principle timing diagram for AMS-scan mode with initial input signal (see Fig.6)". It only differs in its rise time tr and a release of its internal latch when voltage Vt passes the upper threshold between t0 and t1. Now the initial procedure is completed.
The following behaviour does not differ from the description in Section "Description of the principle timing diagram for AMS-latch mode without initial input signal (see Fig.7)".
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
TEA0675
2 +
Vref 0.23 V
handbook, halfpage
+
1 5V
65 65
MBH506
MBH507
Fig.9 Pins 1 and 24: output channel.
Fig.10 Pins 2 and 23: integrating filter.
handbook, halfpage +
3 5V
1.2 k
3.4 k 3.6 k
handbook, halfpage
+
+
4 5V
+ 675 10 k
MBH509
MBH508
Fig.11 Pins 3 and 22: control voltage.
Fig.12 Pins 4 and 21: high-pass filter.
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
handbook, halfpage
5 + 5V
handbook, halfpage
6 + 8V
1 K
MBD510
MBH511
Fig.13 Pins 5 and 20: side chain.
Fig.14 Pin 6: delay time constant.
handbook, halfpage
+
7 5V
handbook, halfpage
+
8 5V
10 k 100 5.8 k 1 pF
MBH513 MBH512
Fig.15 Pins 7 and 18: equalizing output.
Fig.16 Pins 8 and 17: equalizing input.
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
handbook, halfpage
10 5V +
handbook, halfpage
9 10 V
220 100 k
MBH514
12 pF
5V
MBH515
Fig.17 Pin 9: supply voltage.
Fig.18 Pins 10, 12, 13 and 15: input channel.
handbook, halfpage
+
handbook, halfpage
14 8V +
2.5 k 11 5V 2.5 k
MBH516
MBH517
Fig.19 Pin 11: reference voltage.
Fig.20 Pin 14: head switch input.
1996 Jun 07
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Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
handbook, halfpage
+
19 4.6 V
MBH518
Fig.21 Pin 19: AMS output and EQ switch input.
1996 Jun 07
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ndbook, full pagewidth
1996 Jun 07
AMS output NR 4.7 nF 70 s 10 F EQ 10 F ON 1.5 k 20 k 27 k 24 k 10 k 18 k 15 nF OFF 180 k 21 20 19 18 17 16 15 14 13 EQ AMP. PRE AMP. AMS PROCESSOR LOGIC DELAY TIME POWER SUPPLY
Philips Semiconductors
10 F
330 nF
100 nF
output B
270 k
TEST AND APPLICATION INFORMATION
24
23
22
DOLBY B
LATCH AND RISE TIME
TEA0675
Dual Dolby* B-type noise reduction circuit for playback applications
19
EQ AMP. 4 20 k 180 k 15 nF Rt 10 k 4.7 nF 10 F 0.25 V RMS 1 kHz 100 nF ON
(1)
LEVEL DETECTOR
DOLBY B
PRE AMP. 8 9 VCC = 10 V 10 k 1000 F 100 F 10 11 12
1
2
3
5
6
7
270 k 1.5 k OFF 24 k
10 F
output A
330 nF
100 nF
MED629
(1) Switched to VCC for AMS-scan mode.
Preliminary specification
TEA0675
Fig.22 Test circuit for power supply ripple rejection.
1996 Jun 07
handbook, full pagewidth
AMS output 15 nF OFF 10 F ON 1.5 k 20 k 27 k 24 k 10 k 18 k 180 k NR 4.7 nF EQ 70 s 10 F
Philips Semiconductors
10 F
330 nF
100 nF
output B
270 k
24
23
22
21
20
19
18
17
16
15
14
13
DOLBY B
EQ AMP.
PRE AMP.
LATCH AND RISE TIME LOGIC DELAY TIME POWER SUPPLY
AMS PROCESSOR
TEA0675
Dual Dolby* B-type noise reduction circuit for playback applications
20
DOLBY B EQ AMP. 4 20 k 180 k Rt 10 k 10 F 100 nF 10 V 15 nF 4.7 nF 24 k 10 F 5 6 7 8 9 PRE AMP.
LEVEL DETECTOR
1
2
3
10
11
12
270 k
10 F
100 F 200
output A
330 nF
100 nF
MED630
Preliminary specification
TEA0675
Fig.23 Test circuit for channel separation.
handbook, full pagewidth
1996 Jun 07
AMS output 15 nF 10 F 4.7 nF EQ 70 s 10 F 1.5 k 20 k 24 k 10 k 27 k 18 k 21 20 19 18 17 16 15 14 13 EQ AMP. PRE AMP. AMS PROCESSOR LOGIC DELAY TIME POWER SUPPLY
Philips Semiconductors
10 F
330 nF
100 nF
output B
270 k
180 k
24
23
22
DOLBY B
LATCH AND RISE TIME
TEA0675
voltage input
Dual Dolby* B-type noise reduction circuit for playback applications
21
EQ AMP. 4 20 k 15 nF
(1)
LEVEL DETECTOR
DOLBY B
PRE AMP. 8 9 10 11 12
1
2
3
5
6
7
270 k 1.5 k Rt 10 k 10 F 4.7 nF 24 k
10 F
output A
330 nF
100 nF
180 k
100 F 100 nF 10 V
(1) Switched to VCC for AMS-scan mode.
MED631
Preliminary specification
TEA0675
Fig.24 Test circuit for AMS threshold level.
ndbook, full pagewidth
1996 Jun 07
VCC 25 k 10 F Vi 10 F 25 k 27 k AMS output - EQ 70 s 10 F 10 k + 15 nF OFF ON 1.5 k 20 k 24 k 18 k 4.7 nF 180 k NR TP 21 20 19 18 17 16 15 14 13 DOLBY B EQ AMP. PRE AMP. AMS PROCESSOR LOGIC DELAY TIME POWER SUPPLY
Philips Semiconductors
Encode mode
10 F
330 nF
100 nF
output B
270 k
24
23
22
LATCH AND RISE TIME
TEA0675
Dual Dolby* B-type noise reduction circuit for playback applications
22
DOLBY B EQ AMP. 4 20 k 180 k Rt 10 k 10 F TP 100 nF Vi 10 V 15 nF 4.7 nF AMS OFF 24 k VCC 5 6 7 8 9 PRE AMP. 10 F
LEVEL DETECTOR
1
2
3
10
11
12
270 k
10 F
output A
330 nF
100 nF
470 pF
200
100 F
MED632
Decode mode: pre-amplifier 30 dB and EQ amplifier 10 dB linear.
Preliminary specification
TEA0675
Fig.25 Test circuit for frequency response (channel B).
Preliminary specification
TEA0675
Fig.26 EMC test circuit.
handbook, full pagewidth
1996 Jun 07
24 k 4.7 nF 470 pF 20 k 10 k 27 k 200 10 F 200 470 pF 10 F haed-switch input 180 k 15 nF 21 20 19 18 17 16 15 14 13 EQ AMP. PRE AMP. AMS PROCESSOR LOGIC DELAY TIME POWER SUPPLY
Philips Semiconductors
10 F
330 nF
100 nF
output B
270 k
24
23
22
DOLBY B
LATCH AND RISE TIME
TEA0675
Dual Dolby* B-type noise reduction circuit for playback applications
LEVEL DETECTOR
23
EQ AMP. 4 20 k 5 6 7 8 9 VCC = 10 V 10 k 10 F 100 nF 470 pF PRE AMP. 180 k 15 nF 4.7 nF 24 k Rt
MBH497
DOLBY B
1
2
3
10
11
12
270 k
10 F
output A
330 nF
100 nF
200
200 100 F
470 pF
10 40
Decode mode: pre-amplifier 30 dB and EQ amplifier 10 dB linear.
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
LAYOUT OF PRINTED-CIRCUIT BOARD FOR EMC TEST CIRCUIT (FOR TEA0675T)
TEA0675
handbook, full pagewidth
63
52
470 pF 200 200 470 pF 0 0 40 0 0 470 pF 200 200 470 pF
27 k
10 k 20 k 24 k 15 nF 100 nF 180 k 270 k 4.7 nF
100 nF 10
TEA0675T
100 nF
4.7 nF 270 k Rt 180 k 20 k 10 k 100 nF 15 nF 24 k
MBH460
Dimensions in mm.
Fig.27 Top side with components.
1996 Jun 07
24
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
ook, full pagewidth
63
52
10 F 10 F S1 330 nF 100 F MP 100 F X2 X4 X3 MP HFDR. 330 nF MP X1 10 F
10 F
10 F
MBH459
Dimensions in mm.
Fig.28 Bottom side with components.
1996 Jun 07
25
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
PACKAGE OUTLINES SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)
TEA0675
SOT234-1
D seating plane
ME
A2
A
L
A1 c Z e b 24 13 b1 wM (e 1) MH
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 22.3 21.4 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT234-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Jun 07
26
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
TEA0675
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.42 0.39 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.043 0.055 0.016
0.035 0.004 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013AD EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-24
1996 Jun 07
27
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
TEA0675
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Jun 07
28
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TEA0675
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Jun 07
29
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
NOTES
TEA0675
1996 Jun 07
30
Philips Semiconductors
Preliminary specification
Dual Dolby* B-type noise reduction circuit for playback applications
NOTES
TEA0675
1996 Jun 07
31
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com/ps/ (1) ADDRESS CONTENT SOURCE August 6, 1996 SCA49
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands
517021/50/04/pp32 Date of release: 1996 Jun 07 Document order number: 9397 750 00898

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